1. Field of the Invention
The present invention relates to a transfer gate, and more particularly to a transfer gate suitable for an analog switch of the MOS-IC.
2. Description of the Related Art
FIG. 1 shows a circuit diagram of a conventional transfer gate. In the circuit, the current paths of a p-channel MOS FET 41 and an n-channel MOS FET 42 are connected in parallel. For conduction control of those FETs, a gate signal .phi. is applied to the FET 42, and a gate signal .phi. , which is opposite phase with respect to the gate signal .phi., is applied to the gate of the FET 41. When the gate signal .phi. is in a V.sub.SS level and the gate signal .phi. is in a V.sub.DD level, one of the FETs is in an on state irrespective of the level of an input signal Vin applied to an input node 43. Because the combined resistance of the FETs 41 and 42 is very low, if the input signal Vin swings between the voltages V.sub.SS and V.sub.DD, the transfer gate is able to transfer the input signal from the input node 43 to an output node 44, while keeping the voltage level of the input signal substantially constant. The output signal of the transfer gate is denoted as Vout. Consider a case that the gate signal .phi. is in a V.sub.DD level and the gate signal .phi. is in a V.sub.SS level, both the FETs 41 and 42 are in an off state. In this case, the combined resistance of the FETs 41 and 42 is apparently infinity. Accordingly, the transfer gate is unable to transfer the input signal to the output node 44. Because the transfer gate has such a characteristic, the transfer gate shown in FIG. 1 is used mainly as the analog switch of the MOS-IC.
FIG. 2 is a cross sectional view showing the structure of the p-channel MOS FET 41, one of the MOS FETs forming the transfer gate. An n-type well region 52 is formed in a major surface region of a p-type silicon substrate 51. A p-type source region 53, a p-type drain region 54, and an n-type sub-region 55, which are formed in the surface region of the n-type well region 52, are separated from one another by predetermined distances. A gate insulating film 60 is formed on the surface of the substrate 51 (well region 52), while being located between the source and drain regions 53 and 54. A source wire 56 serving as the input node 43 shown in FIG. 1 is led from the source region 53, and a drain wire 57 serving as the output node 44 is led from the drain region 54. The sub-region 55 is for applying a predetermined bias voltage to the well region 52, has an impurity concentration higher than the well region 52, and is connected to the power source V.sub.DD.
The transfer gate containing the p-channel MOS FET 41 thus structured involves the following problem. When the transfer gate is in a cut-off state, viz., the FETs 41 and 42 are both in an off state, if a voltage higher than a predetermined voltage (between the voltages V.sub.SS and V.sub.DD) is applied to the input node 43, the potential at the output node 44 varies. In the transfer gate being in an off state, when the voltage higher than the predetermined voltage is applied to the source wire 56 (input node 43), this high potential is applied to the source region 53. As a result, the source region 53 and the well region 52 are forwardly biased, so that the potential in the well region 52 rises. In turn, the well region 52 and the drain region 54 are reversely biased, so that a depletion layer 59 is generated in the junction between the well region 52 and the drain region 54. As known, the depletion layer 59 is a high resistance region, and shuts off the current flow. When the depletion layer 59 is produced, an imaginary capacitor is brought about (the imaginary capacitor being referred to as a depletion layer capacitor hereinafter). Under this condition, if an alternately varying signal or noise enters the source wire 56 (input node 43), the depletion layer capacitor capacitively couples the well region 52 with the drain region 54. Consequently, the potential of the drain wire 57 (output node 44) varies. As already stated, this type of the transfer gate is generally applied to an analog switch in the MOS-IC. In this case, a plurality of transfer gates are coupled in a parallel fashion. In a specific condition, one of those transfer gates is selected and turned on, while the remaining ones being turned off. Under this condition, if the alternately varying signal enters the input nodes of the transfer gates being in an off state, there is highly probable that the potentials at the output node of the off-state gates vary. A slight variation of the potential at the output node, if occurs, has an adverse effect on the operation of the circuit containing those gates. This is the problem to urgently be solved.